1. Field of the Invention
The present invention generally relates to fault-tolerant computing and more particularly to a fault tolerant or redundant switch architecture.
2. Description of the Related Art
Various aspects of a computer network are of concern to end users, including transmission rates and reliability of data. In addition, in certain applications, such as financial transactions, a computer network is typically designed to be fault-tolerant in certain respects.
In terms of fault tolerance, prior computer systems used completely dual redundant hardware. That is, communication devices such as nodes and switches were incorporated into a computer network, such that if one set of hardware failed, the redundant set could provide the data transmission. For example, Compaq Computer Corp. (the assignee of the present application), uses X and Y planes to provide dual hardware redundancy through a System Area Network (SAN). This computer network system, also known to utilize ServerNet™ technology, utilizes parallel sets of hardware, including communications and storage devices to provide fault tolerant capabilities. This duplication of hardware can be very expensive.
Another type of known fault-tolerant computer system utilizes redundant central processing units (CPUs). CPUs run lock-step with one another wherein one CPU is a master and the other is a slave. Should the master CPU fail, the slave CPU takes over the master's functions. Although this approach requires less hardware than the above dual redundant system, this system only covers faults relating to the CPUs. Although less hardware extensive and thus less expensive, this known approach does not provide overall fault coverage, e.g., fault coverage between a CPU bus and the rest of the network.